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<title>CMSIS-Core (Cortex-A): SCTLR_Type Struct Reference</title>
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   &#160;<span id="projectnumber">Version 1.2.1</span>
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   <div id="projectbrief">CMSIS-Core support for Cortex-A processor-based devices</div>
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<div class="header">
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<a href="#pub-attribs">Data Fields</a>  </div>
  <div class="headertitle">
<div class="title">SCTLR_Type Struct Reference<div class="ingroups"><a class="el" href="group__CMSIS__SCTLR.html">System Control Register (SCTLR)</a></div></div>  </div>
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<div class="contents">

<p>Bit field declaration for SCTLR layout.  
</p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
Data Fields</h2></td></tr>
<tr class="memitem:a21ec59a37644281456a5f607450951d8"><td class="memItemLeft" >struct {</td></tr>
<tr class="memitem:aee870fcf59accda9d93005b885db4e68"><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="unionSCTLR__Type.html#a8cbfde3ba235ebd48e82cb314c9b9cc4">M</a>:1</td></tr>
<tr class="memdesc:aee870fcf59accda9d93005b885db4e68"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 0 MMU enable  <a href="#aee870fcf59accda9d93005b885db4e68">More...</a><br/></td></tr>
<tr class="separator:aee870fcf59accda9d93005b885db4e68"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9492fdd4500a9a7e596c0bf159017a38"><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="unionSCTLR__Type.html#a078edcb9c3fc8b46b8cf382ad249bb79">A</a>:1</td></tr>
<tr class="memdesc:a9492fdd4500a9a7e596c0bf159017a38"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 1 Alignment check enable  <a href="#a9492fdd4500a9a7e596c0bf159017a38">More...</a><br/></td></tr>
<tr class="separator:a9492fdd4500a9a7e596c0bf159017a38"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aad882f21882a931a26abae1731600052"><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="unionSCTLR__Type.html#a122a4dde5ab1a27855ddad88bb3f9f78">C</a>:1</td></tr>
<tr class="memdesc:aad882f21882a931a26abae1731600052"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 2 Cache enable  <a href="#aad882f21882a931a26abae1731600052">More...</a><br/></td></tr>
<tr class="separator:aad882f21882a931a26abae1731600052"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac59e580e268394e9e90a095c16563a9e"><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="unionSCTLR__Type.html#a98b55213f3bf0a8bd4f1db90512238de">CP15BEN</a>:1</td></tr>
<tr class="memdesc:ac59e580e268394e9e90a095c16563a9e"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 5 CP15 barrier enable  <a href="#ac59e580e268394e9e90a095c16563a9e">More...</a><br/></td></tr>
<tr class="separator:ac59e580e268394e9e90a095c16563a9e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a90c07e688b7dd59e8573d9713a28e918"><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="unionSCTLR__Type.html#a805ee3324a333d7a77d9f0d8f0fac9a7">B</a>:1</td></tr>
<tr class="memdesc:a90c07e688b7dd59e8573d9713a28e918"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 7 Endianness model  <a href="#a90c07e688b7dd59e8573d9713a28e918">More...</a><br/></td></tr>
<tr class="separator:a90c07e688b7dd59e8573d9713a28e918"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8ee8275c8955af4214a3cd30964d9d4c"><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="unionSCTLR__Type.html#a6598f817304ccaef4509843ce041de1c">SW</a>:1</td></tr>
<tr class="memdesc:a8ee8275c8955af4214a3cd30964d9d4c"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 10 SWP and SWPB enable  <a href="#a8ee8275c8955af4214a3cd30964d9d4c">More...</a><br/></td></tr>
<tr class="separator:a8ee8275c8955af4214a3cd30964d9d4c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a09f1b3d0c58bd829eede242dc4aa7742"><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="unionSCTLR__Type.html#a37f6910db32361f44a268f93b9ff7b20">Z</a>:1</td></tr>
<tr class="memdesc:a09f1b3d0c58bd829eede242dc4aa7742"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 11 Branch prediction enable  <a href="#a09f1b3d0c58bd829eede242dc4aa7742">More...</a><br/></td></tr>
<tr class="separator:a09f1b3d0c58bd829eede242dc4aa7742"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3a66d2af2ed13e551f9cf5251296da27"><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="unionSCTLR__Type.html#a0a4ed1a41f25a191cf4a500401c3c5db">I</a>:1</td></tr>
<tr class="memdesc:a3a66d2af2ed13e551f9cf5251296da27"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 12 Instruction cache enable  <a href="#a3a66d2af2ed13e551f9cf5251296da27">More...</a><br/></td></tr>
<tr class="separator:a3a66d2af2ed13e551f9cf5251296da27"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac3255ae7d32a953d8b590e8b04c88439"><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="unionSCTLR__Type.html#a9a3885d0e2ba2433d128f62ec2552a00">V</a>:1</td></tr>
<tr class="memdesc:ac3255ae7d32a953d8b590e8b04c88439"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 13 Vectors bit  <a href="#ac3255ae7d32a953d8b590e8b04c88439">More...</a><br/></td></tr>
<tr class="separator:ac3255ae7d32a953d8b590e8b04c88439"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a20926a14c1963b5faa47f39743b4be86"><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="unionSCTLR__Type.html#a10212a8d038bb1e076cbd06a5ba0b055">RR</a>:1</td></tr>
<tr class="memdesc:a20926a14c1963b5faa47f39743b4be86"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 14 Round Robin select  <a href="#a20926a14c1963b5faa47f39743b4be86">More...</a><br/></td></tr>
<tr class="separator:a20926a14c1963b5faa47f39743b4be86"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a502e8aceb66e14fe2a77a08da124f450"><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="unionSCTLR__Type.html#aba2a8aac3478cdc34428af7b9726d97f">HA</a>:1</td></tr>
<tr class="memdesc:a502e8aceb66e14fe2a77a08da124f450"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 17 Hardware Access flag enable  <a href="#a502e8aceb66e14fe2a77a08da124f450">More...</a><br/></td></tr>
<tr class="separator:a502e8aceb66e14fe2a77a08da124f450"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aefd070d6ee9f3513bcce13f5be0599a4"><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="unionSCTLR__Type.html#a551d0505856acaef4dd1ecca54cb540d">WXN</a>:1</td></tr>
<tr class="memdesc:aefd070d6ee9f3513bcce13f5be0599a4"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 19 Write permission implies XN  <a href="#aefd070d6ee9f3513bcce13f5be0599a4">More...</a><br/></td></tr>
<tr class="separator:aefd070d6ee9f3513bcce13f5be0599a4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4998de3b09d2c15b8facd4f0f3274616"><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="unionSCTLR__Type.html#a32873e90e6814c3a2fc1b1c79c0bc8c8">UWXN</a>:1</td></tr>
<tr class="memdesc:a4998de3b09d2c15b8facd4f0f3274616"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 20 Unprivileged write permission implies PL1 XN  <a href="#a4998de3b09d2c15b8facd4f0f3274616">More...</a><br/></td></tr>
<tr class="separator:a4998de3b09d2c15b8facd4f0f3274616"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5baee3d49f17ae03176bec8340bd4d59"><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="unionSCTLR__Type.html#afe77b6c5d73e64d4ef3c5dc5ce2692dc">FI</a>:1</td></tr>
<tr class="memdesc:a5baee3d49f17ae03176bec8340bd4d59"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 21 Fast interrupts configuration enable  <a href="#a5baee3d49f17ae03176bec8340bd4d59">More...</a><br/></td></tr>
<tr class="separator:a5baee3d49f17ae03176bec8340bd4d59"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1cd17f69c735dd44c7f07738a4da7b47"><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="unionSCTLR__Type.html#a1ca6569db52bca6250afbbd565d05449">U</a>:1</td></tr>
<tr class="memdesc:a1cd17f69c735dd44c7f07738a4da7b47"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 22 Alignment model  <a href="#a1cd17f69c735dd44c7f07738a4da7b47">More...</a><br/></td></tr>
<tr class="separator:a1cd17f69c735dd44c7f07738a4da7b47"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6f7a63c4c3902ef2f9efa30788b3df7c"><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="unionSCTLR__Type.html#af29c170c65dd4d076b78c793dc17aa0a">VE</a>:1</td></tr>
<tr class="memdesc:a6f7a63c4c3902ef2f9efa30788b3df7c"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 24 Interrupt Vectors Enable  <a href="#a6f7a63c4c3902ef2f9efa30788b3df7c">More...</a><br/></td></tr>
<tr class="separator:a6f7a63c4c3902ef2f9efa30788b3df7c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab23af569bdda48e5e10e649c33e7a18b"><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="unionSCTLR__Type.html#af868e042d01b612649539c151f1aaea5">EE</a>:1</td></tr>
<tr class="memdesc:ab23af569bdda48e5e10e649c33e7a18b"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 25 Exception Endianness  <a href="#ab23af569bdda48e5e10e649c33e7a18b">More...</a><br/></td></tr>
<tr class="separator:ab23af569bdda48e5e10e649c33e7a18b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1f782067130fabb7871ab5e81846024d"><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="unionSCTLR__Type.html#a60d589567422115a14d6d0fde342dfce">NMFI</a>:1</td></tr>
<tr class="memdesc:a1f782067130fabb7871ab5e81846024d"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 27 Non-maskable FIQ (NMFI) support  <a href="#a1f782067130fabb7871ab5e81846024d">More...</a><br/></td></tr>
<tr class="separator:a1f782067130fabb7871ab5e81846024d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a09f921ddcda22ce695c9f9074370c70c"><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="unionSCTLR__Type.html#abc3055203ce7f9d117ceb10f146722f3">TRE</a>:1</td></tr>
<tr class="memdesc:a09f921ddcda22ce695c9f9074370c70c"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 28 TEX remap enable.  <a href="#a09f921ddcda22ce695c9f9074370c70c">More...</a><br/></td></tr>
<tr class="separator:a09f921ddcda22ce695c9f9074370c70c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a375f85e72f3f61f58dbe4763d58c77e7"><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="unionSCTLR__Type.html#ae5a729bf64a6de4cbfa42c1a7d254535">AFE</a>:1</td></tr>
<tr class="memdesc:a375f85e72f3f61f58dbe4763d58c77e7"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 29 Access flag enable  <a href="#a375f85e72f3f61f58dbe4763d58c77e7">More...</a><br/></td></tr>
<tr class="separator:a375f85e72f3f61f58dbe4763d58c77e7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac58fc5f8b7d0bf6311410c23cb5fb28d"><td class="memItemLeft" >&#160;&#160;&#160;uint32_t&#160;&#160;&#160;<a class="el" href="unionSCTLR__Type.html#a25d4c4cf4df168a30cc4600a130580ab">TE</a>:1</td></tr>
<tr class="memdesc:ac58fc5f8b7d0bf6311410c23cb5fb28d"><td class="mdescLeft">&#160;</td><td class="mdescRight">bit: 30 Thumb Exception enable  <a href="#ac58fc5f8b7d0bf6311410c23cb5fb28d">More...</a><br/></td></tr>
<tr class="separator:ac58fc5f8b7d0bf6311410c23cb5fb28d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a21ec59a37644281456a5f607450951d8"><td class="memItemLeft" valign="top">}&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionSCTLR__Type.html#a21ec59a37644281456a5f607450951d8">b</a></td></tr>
<tr class="memdesc:a21ec59a37644281456a5f607450951d8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Structure used for bit access.  <a href="#a21ec59a37644281456a5f607450951d8">More...</a><br/></td></tr>
<tr class="separator:a21ec59a37644281456a5f607450951d8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4cb084e09742794f1d040c4e44ee4e0f"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionSCTLR__Type.html#a4cb084e09742794f1d040c4e44ee4e0f">w</a></td></tr>
<tr class="memdesc:a4cb084e09742794f1d040c4e44ee4e0f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Type used for word access.  <a href="#a4cb084e09742794f1d040c4e44ee4e0f">More...</a><br/></td></tr>
<tr class="separator:a4cb084e09742794f1d040c4e44ee4e0f"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table>
<h2 class="groupheader">Field Documentation</h2>
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          <td class="memname">uint32_t SCTLR_Type::A</td>
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